1. Field of the Invention
The present invention relates to a method for forming a floating gate structure for a flash memory, and more particularly to a method for forming a smooth floating gate structure for a flash memory.
2. Description of the Related Art
Non-volatile semiconductor memory devices, such as EEPROM and xe2x80x9cflashxe2x80x9d devices, are both electrically erasable and writable (or programmable). Such devices retain data even after power is shut down. Similarly, erasable programmable logic integrated circuits (EPLD, or PLD) use non-volatile memory cells to achieve certain reprogrammable logic functions. Non-volatile memory devices and PLDs, have a limited lifetime due to the endurance related stress such devices suffer each time they go through a program-erase cycle. The endurance of such devices is its ability to withstand a given number of program-erase cycles.
A main component of a cell of a non-volatile memory device or a PLD, is a floating gate, in a field effect transistor structure, disposed over but insulated from a channel region which is disposed between a source region and a drain region in a semiconductor substrate. A control or select gate is generally disposed over the floating gate, and is insulated therefrom by a dielectric layer. Alternatively, a control xe2x80x9cgatexe2x80x9d can be implemented by an adjacent diffused region of the substrate that is also insulated from the floating gate. The floating gate is, therefore, surrounded by an electrically insulating dielectric.
The threshold voltage is the minimum amount of voltage that must be applied to the control gate before the transistor is turned xe2x80x9conxe2x80x9d to permit conduction between its source and drain regions, and is a function of the level of charge on the floating gate. The control gate acts as a word line to enable reading or writing of a single selected cell in a two-dimensional array of cells (i.e., a non-volatile memory device or PLD). A cell is xe2x80x9cerasedxe2x80x9d by holding the control gate and its source and drain regions at appropriate voltages so that electrons travel from the substrate through an intervening oxide layer (i.e., a tunnel oxide layer or a tunnel oxide) and onto the floating gate. If enough electrons are collected on the floating gate, the conductivity of the channel of the field effect transistor of the cell is changed. By measuring the conductivity of the cell, it is determined whether a binary xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is being stored. Since the floating gate of the cell is well insulated, the cell is not volatile and retains its charge for an indefinite period without any power being applied to it.
A cell or group of cells in a non-volatile memory device or a PLD, are also xe2x80x9cprogrammable.xe2x80x9d During programming, the control gate, the source and the drain regions, of a cell are held at a potential that causes electrons to move back through the tunnel oxide and into the substrate, usually the source region of the substrate. This movement reverses the effect of an earlier erase operation.
Reliability assurance is a costly, time consuming, difficult and important task in integrated circuit (IC) development and production. This is particularly true with non-volatile memory devices and PLDs. Such devices are subject to the usual IC failure mechanisms such as package and bonding failures, electrostatic discharge, electromigration, oxide breakdown, etc. Additionally, such devices must meet other reliability requirements. For example, they must retain data for ten years and must function normally (within specifications) after repeated program and erase operations, i.e., program-erase cycles.
FIGS. 1A-1F show a process flow of a conventional method for forming a floating gate of a flash memory. As shown in FIG. 1A, a tunnel oxide 106, a polysilicon layer 102 (the first floating gate layer), a pad SiN layer 104 and a photoresist layer 108 are formed on a Si substrate 100. The photoresist layer 108 is then patterned to expose the pad SiN layer 104. The pad SiN layer 104, the polysilicon layer 102, the tunnel oxide 106 and the Si substrate 100 are then etched to form trenches, and the trenches are filled with a dielectric layer 110 to form shallow trench isolations (STI) as shown in FIG. 1B. The pad SiN layer 104 is removed and the dielectric layer 110 is etched to the surface level of the polysilicon layer 102. A polysilicon layer 112 (the second floating gate layer) and a pad SiN layer 114 are formed as shown in FIG. 1C. A floating gate pattern is formed into the pad SiN layer 114 and the second polysilicon layer 112. A SiN layer 116 is formed and is then etched to form SiN spacers as shown in FIG. ID. The second polysilicon layer 112 is then etched to expose the dielectric layer 110 or the STI in FIG. 1E. The pad SiN layer. 114 and the SiN layer 116 are removed and the floating gate is formed in FIG. 1F. The profile of the floating gate shown in FIG. 1F has many corners which would cause charge loss amid alternatively programming and erasing the floating gate, i.e., program-erase cycling thereby degrading the retention time and the reliability of this conventional flash memory. Moreover, theses. undesired corners also affect the word line topology of this conventional flash memory.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The advantages of this invention are that it solves the problems mentioned above.
It is therefore an object of the invention to provide a method for forming a floating gate structure of a flash memory which can eliminate the floating gate corner effect.
It is another object of this invention to provide a smooth floating gate structure of a flash memory.
It is a further object of this invention to provide a reliable floating gate structure of a flash memory having superior charge retention characteristics.
To achieve these objects, and in accordance with the purpose of the invention, the invention provides a method for forming a floating gate structure of a flash memory. The method comprises the following steps. A substrate is firstly provided, and a first conductive layer and a second conductive layer are sequentially formed on the substrate. A first dielectric layer is then formed on the second conductive layer. A first hard mask layer and a second hard mask layer are formed sequentially on the first dielectric layer. A floating gate pattern is then transferred into the second hard mask layer to expose the first hard mask layer. The first hard mask layer is then etched to form a pattern and expose the first dielectric layer. A second dielectric layer conformally formed over the second hard mask layer and the pattern. The second dielectric layer is etched back to form a spacer and expose the first dielectric layer. The first dielectric layer is then etched to expose the second conductive layer and the spacer, the second hard mask layer, the first, hard mask layer and the first dielectric layer are finally removed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.